Semiconductor memory devices are generally classified into volatile memory devices (e.g., DRAMs and SRAMs) and nonvolatile memory devices (e.g., EEPROMs, FRAMs, PRAMs, MRAMs, and flash memories). A volatile memory device loses data stored therein when power supply thereto is interrupted, whereas a nonvolatile memory device retains data stored therein even when power supply thereto is interrupted. In particular, a flash memory device is widely used as a storage medium in a computer system because of its high program speed, low power consumption and large data storage capacity.
In the flash memory device, data states storable in each memory cell may be determined according to the number of bits stored in the memory cell. A memory cell storing 1-bit data per cell is called a single-bit cell or a single-level cell (SLC), and a memory cell storing multi-bit data (i.e., at least 2-bit data) per cell is called a multi-bit cell, a multi-level cell (MLC) or a multi-state cell. The multi-bit cell is advantageous for high integration. However, as the number of bits programmed in each memory cell increase, the reliability decreases and the read failure rate increases.
For example, if k bits are to be programmed in a memory cell, one of 2k threshold voltages must be formed in the memory cell. Due to the minute difference between the electrical characteristics of memory cells, the threshold voltages of memory cells programmed with the same data may form a predetermined range of threshold voltage distribution. Threshold voltage distributions may correspond respectively to 2k data values that may be generated by k bits.
However, a voltage window available for threshold voltage distributions is limited. Therefore, as the value k increases, the distance between the threshold voltage distributions decreases and the adjacent threshold voltage distributions may overlap each other. As the adjacent threshold voltage distributions overlap each other, read data may include a number of error bits (e.g., several error bits or several tens of error bits). What is therefore required is a scheme for efficiently detecting/correcting a read error in data read from a flash memory device that stores multi-bit data.